parameter：
|
Applications |
General Purpose |
|
# of TX/RX |
2T2R |
|
# of DUCs/TX |
2 |
|
# of DDCs/RX |
2 |
|
Data rate (MSPS) |
500 |
|
RF frequency (Max) (MHz) |
7400 |
|
RF frequency (Min) (MHz) |
5 |
|
Operating temperature range (C) |
-40 to 85 |
Package | pin | size：
|
FCBGA (ABJ) |
400 |
289 mm² 17 x 17 |
|
FCBGA (ALK) |
400 |
289 mm² 17 x 17 |
characteristic：
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Dual channel RF sampling 12 GSPS transmit DAC
Dual channel RF sampling 3 GSPS receiving ADC
Upper limit of bandwidth per TX or RX signal: 400 MHz
RF frequency range: 5 MHz to 7.4 GHz
Digital step attenuator (DSA):
Tx:40 dB range, 0.125 DB step
Rx/fb:25 dB range, 0.5 dB step
Single band or dual band duc/ddc for TX and RX
16 NCOs per tx/rx and FB
Optional internal pll/vco, providing dac/adc clock or external clock at DAC or ADC sampling rate
Sysref alignment detector
Serializer / deserializer data interface:
Compatible with jesd204b and jesd204c
8 serializer / deserializer transceivers up to 29.5 Gbps
Subclass 1 Multi device synchronization
Package: 17mm × 17mm FCBGA with spacing of 0.8 mm
explain:
Afe7903 is a high-performance, broadband, multi-channel transceiver, which integrates two RF sampling transmission chains and two RF sampling reception chains. This device has an operating frequency of up to 7.4 GHz and supports RF sampling directly in the HF, VHF, UHF, l, s and C band frequency range without additional frequency conversion stages. The improvement of density and flexibility has realized the support of high channel number and multi task system.
TX signal path supports interpolation and digital up conversion options, providing signal bandwidth up to 400 MHz. The output of the Duc drives the 12 GSPS DAC (digital to analog converter) to enhance operation in the second Nyquist region through the mixed mode output option. The DAC output includes a variable gain amplifier (TX DSA) with a 40 dB range and 1 dB analog and 0.125 DB digital stepping.
blank
Each receiver chain contains a 25 dB range DSA (Digital step attenuator), followed by a 3 GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power consumption detector and various digital power consumption detectors to facilitate the implementation of external or internal autonomous AGC. In addition, it also has a RF overload detector to provide device reliability protection. Flexible decimation options provide data bandwidth optimization up to 400 MHz (for two rxs).
The device includes a sysref timing detector to optimize the sysref input timing relative to the device clock.
Picture display：
